When exporting a 3D model of a board design to the MCAD domain it may be desirable to exclude freely placed 3D body models, such as an enclosure that has been previously imported from MCAD.

The center point in a line between two snap points (Spacebar mode).

The 90° locations (points crossing the orthogonal axes) around a hole circle.

The enhanced snapping location options also improve the ability to measure critical span distances in 3D objects. To improve the convenience and accuracy of positioning 3D models in a PCB design, support has been added for a range of new snapping point placement options for 3D models. Along with allowing back drilling from the board surface to any internal layer, the process and its Design Rule now recognizes layer connections made to copper objects such as polygons, fills and regions. Control over the handling of the Diff Pair Net classes can be specified in the Comparator and ECO tabs of the Options for PCB project dialog ( Project » Project Options).Ĭontrolled Depth Drilling, or Back Drilling, in Altium Designer has been improved to support the PCB Via stub removal technique for any defined Back Drill Pairs. When passed to the PCB via an Engineering Change Order (ECO), the class becomes available as a Diff Pair Class to apply to PCB Differential Pair Routing Rules. Updates Create Differential Pair classes in the Schematic EditorĪ dedicated Differential Pair Class can now be defined at the schematic level by adding the new Diff.PairNetClass class type to Differential Pair Directives through the Properties panel. ► See the FPGA Pin Mapper Quick Guide for an overview of using the Pin Mapping feature. The pin data exchange between the domains is therefore bidirectional, which enables an iterative and cooperative approach to FPGA pin layout through pin swapping, while avoiding the errors of manually passing pin data between domains. Altium Designer will detect any changes made to that file and offer a range of pin data synchronization choices, including the option to update the external file to match the net pin names in Altium Designer. Included in Altium Designer as the Pin Mapper dialog, it allows a link to be specified between a schematic component and an external *.csv pin information file that has been generated by the FPGA tool.

It offers an interactive mechanism for exchanging pin/net definition data between the FPGA (or Microcontroller) and PCB domains via the common format of csv pin report/information files. The FPGA Pin Mapping feature has been developed to expedite the process of achieving the optimal topology for pin programmable devices in PCB layouts.

The FPGA Pin Mapper is currently a beta version.

Update to altium designer 18